Counter Modes; Figure 26. Counter Timing Diagram With Prescaler Division Change From 1 To 2; Figure 27. Counter Timing Diagram With Prescaler Division Change From 1 To 4 - ST STM32F101 Series Reference Manual

RM0008

Figure 26. Counter timing diagram with prescaler division change from 1 to 2

Figure 27. Counter timing diagram with prescaler division change from 1 to 4

12.4.2

Counter modes

Upcounting mode
In upcounting mode, the counter counts from 0 to the auto-reload value (content of the
TIM1_ARR register), then restarts from 0 and generates a counter overflow event.
If the repetition counter is used, the update event (UEV) is generated after upcounting is
repeated for the number of times programmed in the repetition counter register
(TIM1_RCR). Else the update event is generated at each counter overflow.
Setting the UG bit in the TIM1_EGR register (by software or by using the slave mode
controller) also generates an update event.
The UEV event can be disabled by software by setting the UDIS bit in the TIM1_CR1
register. This is to avoid updating the shadow registers while writing new values in the
CK_PSC
CNT_EN
Timer clock = CK_CNT
Counter register
Update event (UEV)
Prescaler control register
Write a new value in TIM1_PSC
Prescaler buffer
Prescaler counter
CK_PSC
CNT_EN
Timer clock = CK_CNT
Counter register
Update event (UEV)
Prescaler control register
Write a new value in TIM1_PSC
Prescaler buffer
Prescaler counter
Advanced control timer (TIM1)
F7 F8 F9 FA FB FC 00
0
0
0 0 1
F7 F8 F9 FA FB FC
0
0
0 1
0
01 02 03
1
1
0 1 0 1 0 1
00 01
3
3
2 3 0 1 2 3
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