ST STM32F101 Series Reference Manual page 416

Serial peripheral interface (SPI)
If CPHA (clock phase) bit is set, the second edge on the SCK pin (falling edge if the CPOL
bit is reset, rising edge if the CPOL bit is set) is the MSBit capture strobe. Data is latched on
the occurrence of the first clock transition. If CPHA bit is reset, the first edge on the SCK pin
(falling edge if CPOL bit is set, rising edge if CPOL bit is reset) is the MSBit capture strobe.
Data is latched on the occurrence of the second clock transition.
The combination of the CPOL clock polarity and CPHA (clock phase) bits selects the data
capture clock edge.
Figure 164, shows an SPI transfer with the four combinations of the CPHA and CPOL bits.
The diagram may be interpreted as a master or slave timing diagram where the SCK pin, the
MISO pin, the MOSI pin are directly connected between the master and the slave device.
Note: 1 Prior to changing the CPOL/CPHA bits the SPI must be disabled by resetting the SPE bit.
2 Master and slave must be programmed with the same timing mode.
3 The idle state of SCK must correspond to the polarity selected in the SPI_CR1 register (by
pulling up SCK if CPOL=1 or pulling down SCK if CPOL=0).
4 The Data Frame Format (8- or 16-bit) is selected through the DFF bit in SPI_CR1 register,
and determines the data length during transmission/reception.
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