How To Program The Watchdog Timeout; Figure 23. Watchdog Block Diagram - ST STM32F101 Series Reference Manual

Window watchdog (WWDG)

Figure 23. Watchdog block diagram

RESET
The application program must write in the WWDG_CR register at regular intervals during
normal operation to prevent an MCU reset. This operation must occur only when the counter
value is lower than the window register value. The value to be stored in the WWDG_CR
register must be between 0xFF and 0xC0:
Enabling the watchdog:
The watchdog is always disabled after a reset. It is enabled by setting the WDGA bit in
the WWDG_CR register, then it cannot be disabled again except by a reset.
Controlling the downcounter:
This downcounter is free-running: It counts down even if the watchdog is disabled.
When the watchdog is enabled, the T6 bit must be set to prevent generating an
immediate reset.
The T[5:0] bits contain the number of increments which represents the time delay
before the watchdog produces a reset. The timing varies between a minimum and a
maximum value due to the unknown status of the prescaler when writing to the
WWDG_CR register (see
The Configuration register (WWDG_CFR) contains the high limit of the window: To
prevent a reset, the downcounter must be reloaded when its value is lower than the
window register value and greater than 0x3F.
watchdog process.
Another way to reload the counter is to use the early wakeup interrupt (EWI). This
interrupt is enabled by setting the EWI bit in the WWDG_CFR register. When the
downcounter reaches the value 40h, this interrupt is generated and the corresponding
interrupt service routine (ISR) can be used to reload the counter to prevent WWDG
reset.
This interrupt is cleared by writing '0' to the EWIF bit in the WWDG_SR register.
Note: The T6 bit can be used to generate a software reset (the WDGA bit is set and the T6 bit is
cleared).
11.4

How to program the watchdog timeout

Figure 24
Watchdog Counter (CNT) and the resulting timeout duration in milliseconds. This can be
144/501
comparator
= 1 when
T6:0 > W6:0
Write WWDG_CR
PCLK1
(from RCC clock controller)
Figure
shows the linear relationship between the 6-bit value to be loaded in the
Watchdog Configuration Register (WWDG_CFR)
- W5
W6 W4
CMP
Watchdog Control Register (WWDG_CR)
WDGA T5
T6 T4
6-bit downcounter (CNT)
WDG prescaler
24).
Figure 24
W0
W2 W1
W3
T1 T0
T3 T2
(WDGTB)
describes the window
RM0008