RM0008
20.4.4
Using serial wire and releasing the unused debug pins as GPIOs
To use the serial wire DP to release some GPIOs, the user software must set
SWJ_CFG=010 just after reset. This release PA15, PB3 and PB4 which now become
available as GPIOs.
When debugging, the host performs the following actions:
Under system RESET, all SWJ pins are assigned (JTAG-DP + SW-DP)
Under system RESET, the debugger host sends the JTAG sequence to switch from the
JTAG-DP to the SW-DP.
Still under system RESET, the debugger sets a breakpoint on vector reset
The System Reset is released and the Core halts.
All the debug communications from this point are done using the SW-DP. The other
JTAG pins can then be reassigned as GPIOs by the user software.
Note:
For user software designs, note that:
To release the debug pins, remember that they will be first configured either in input-pull-up
(nTRST, TMS, TDI) or pull-down (TCK) or output tristate (TDO) for a certain duration after
reset until the instant when the user software releases the pins.
When debug pins (JTAG or SW or TRACE) are mapped, changing the corresponding I/O pin
configuration in the IOPORT controller has no effect.
20.5
STM32F10xxx JTAG TAP connection
The STM32F10xxx MCU integrates two serially-connected JTAG TAPs, the TMC TAP
dedicated for Test (IR is 5-bit wide) and the Cortex-M3 TAP (IR is 4-bits wide).
To access the TAP of the Cortex-M3 for debug purposes:
1.
First, it is necessary to shift the BYPASS instruction of the TMC TAP.
2.
Then, for each IR shift, the scan chain contains 9 bits (=5+4) and the unused TAP
instruction must be shifted in using the BYPASS instruction.
3.
For each data shift, the unused TAP, which is in BYPASS mode, adds 1 extra data bit in
the data scan chain.
Note:
Important: Once Serial-Wire is selected using the dedicated ARM JTAG sequence, the
TMC TAP is automatically disabled (JTMS forced high).
Debug support (DBG)
473/501
Need help?
Do you have a question about the STM32F101 Series and is the answer not in the manual?