Dma Interrupt Flag Clear Register (Dma - ST STM32F101 Series Reference Manual

DMA controller (DMA)
Bits 25, 21, TCIFx: Channel x Transfer Complete flag (x = 1 ..7)
17, 13, 9, 5,
This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the
1
DMA_IFCR register.
0: No transfer complete (TC) event on channel x
1: A transfer complete (TC) event occurred on channel x
Bits 24, 20, GIFx: Channel x Global interrupt flag (x = 1 ..7)
16, 12, 8, 4,
This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the
0
DMA_IFCR register.
0: No TE, HT or TC event on channel x
1: A TE, HT or TC event occurred on channel x
7.4.2 DMA interrupt flag clear register (DMA_IFCR)
Address offset: 0x04
Reset value: 0x0000 0000
31 30 29 28
Reserved
15 14 13 12
CTEIF CHTIF CTCIF CGIF
4 4 4
rw rw rw rw
Bits 31:28 Reserved, always read as 0.
Bits 27, 23, CTEIFx: Channel x Transfer Error clear (x = 1 ..7)
19, 15, 11,
This bit is set and cleared by software.
7, 3
0: No effect
1: Clears the corresponding TEIF flag in the DMA_ISR register
Bits 26, 22, CHTIFx: Channel x Half Transfer clear (x = 1 ..7)
18, 14, 10,
This bit is set and cleared by software.
6, 2
0: No effect
1: Clears the corresponding HTIF flag in the DMA_ISR register
Bits 25, 21, CTCIFx: Channel x Transfer Complete clear (x = 1 ..7)
17, 13, 9, 5,
This bit is set and cleared by software.
1
0: No effect
1: Clears the corresponding TCIF flag in the DMA_ISR register
Bits 24, 20, CGIFx: Channel x Global interrupt clear (x = 1 ..7)
16, 12, 8, 4,
This bit is set and cleared by software.
0
0: No effect
1: Clears the GIF, TEIF, HTIF and TCIF flags in the DMA_ISR register
114/501
27 26 25
CTEIF CHTIF CTCIF
7 7 7
rw rw rw
11 10 9
CTEIF CHTIF CTCIF
4 3 3 3
rw rw rw
24 23 22 21
CGIF CTEIF CHTIF CTCIF
7 6 6
rw rw rw rw
8 7 6
CGIF CTEIF CHTIF CTCIF
3 2 2
rw rw rw rw
20 19 18
CGIF CTEIF CHTIF
6 6 5 5
rw rw rw
5 4 3 2
CGIF CTEIF CHTIF
2 2 1 1
rw rw rw
RM0008
17 16
CTCIF CGIF
5 5
rw rw
1 0
CTCIF CGIF
1 1
rw rw