Iwdg Register Description; Key Register (Iwdg_Kr); Prescaler Register (Iwdg_Pr) - ST STM32F101 Series Reference Manual

RM0008
10.2

IWDG register description

Refer to
10.2.1

Key register (IWDG_KR)

Address offset: 0x00
Reset value: 0x0000 0000 (reset by Standby mode)
31 30 29 28
15 14 13 12
w w w
Bits 31:16 Reserved, read as 0.
Bits 15:0 KEY[15:0]: Key value (write only, read 0000h)
These bits must be written by software at regular intervals with the key value AAAAh, otherwise the
watchdog generates a reset when the counter reaches 0.
Writing the key value 5555h to enables access to the IWDG_PR and IWDG_RLR registers (see
Section
Writing the key value CCCCh starts the watchdog (except if the hardware watchdog option is
selected)
10.2.2

Prescaler register (IWDG_PR)

Address offset: 0x04
Reset value: 0x0000 0000
31 30 29 28
15 14 13 12
Bits 31:3 Reserved, read as 0.
Section 1.1 on page 23
27 26 25
11 10 9
w w w w
10.1.2)
27 26 25
11 10 9
Reserved
for a list of abbreviations used in register descriptions.
24 23 22
Reserved
8 7 6
KEY[15:0]
w w w
24 23 22
Reserved
8 7 6
Independent watchdog (IWDG)
21 20 19 18
5 4 3 2
w w w w
21 20 19 18
5 4 3 2
rw
17 16
1 0
w w
17 16
1 0
PR[2:0]
rw rw
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