Status Register (Iwdg_Sr) - ST STM32F101 Series Reference Manual

RM0008
10.2.4

Status register (IWDG_SR)

Address offset: 0x0C
Reset value: 0x0000 0000 (not reset by Standby mode)
31 30 29 28
15 14 13 12
Bits 31:2 Reserved
Bit 1 RVU: Watchdog counter reload value update
This bit is set by hardware to indicate that an update of the reload value is ongoing. It is reset by
hardware when the reload value update operation is completed in the V
to 5 RC 40 kHz cycles).
Reload value can be updated only when RVU bit is reset.
Bit 0 PVU: Watchdog prescaler value update
This bit is set by hardware to indicate that an update of the prescaler value is ongoing. It is reset by
hardware when the prescaler update operation is completed in the V
RC 40 kHz cycles).
Prescaler value can be updated only when PVU bit is reset.
Note: If several reload values or prescaler values are used by application, it is mandatory to wait
until RVU bit is reset before changing the reload value and to wait until PVU bit is reset
before changing the prescaler value. However, after updating the prescaler and/or the
reload value it is not necessary to wait until RVU or PVU is reset before continuing code
execution (even in case of low-power mode entry, the write operation is taken into account
and will complete)
27 26 25 24
Reserved
11 10 9 8
Reserved
Independent watchdog (IWDG)
23 22 21 20
7 6 5 4
DD
19 18 17
3 2 1
RVU
r
voltage domain (takes up
DD
voltage domain (takes up to 5
141/501
16
0
PVU
r