ST STM32F101 Series Reference Manual page 390

USB full speed device interface (USB)
OUT and SETUP packets (data reception)
These two tokens are handled by the USB peripheral more or less in the same way; the
differences in the handling of SETUP packets are detailed in the following paragraph about
control transfers. When receiving an OUT/SETUP PID, if the address matches a valid
endpoint, the USB peripheral accesses the contents of the ADDRn_RX and COUNTn_RX
locations inside the buffer descriptor table entry related to the addressed endpoint. The
content of the ADDRn_RX is stored directly in its internal register ADDR. While COUNT is
now reset and the values of BL_SIZE and NUM_BLOCK bit fields, which are read within
COUNTn_RX content are used to initialize BUF_COUNT, an internal 16 bit counter, which is
used to check the buffer overrun condition (all these internal registers are not accessible by
software). Data bytes subsequently received by the USB peripheral are packed in words
(the first byte received is stored as least significant byte) and then transferred to the packet
buffer starting from the address contained in the internal ADDR register while BUF_COUNT
is decremented and COUNT is incremented at each byte transfer. When the end of DATA
packet is detected, the correctness of the received CRC is tested and only if no errors
occurred during the reception, an ACK handshake packet is sent back to the transmitting
host. In case of wrong CRC or other kinds of errors (bit-stuff violations, frame errors, etc.),
data bytes are still copied in the packet memory buffer, at least until the error detection point,
but ACK packet is not sent and the ERR bit in register is set. However, there is usually no
software action required in this case: the USB peripheral recovers from reception errors and
remains ready for the next transaction to come. If the addressed endpoint is not valid, a NAK
or STALL handshake packet is sent instead of the ACK, according to bits STAT_RX in the
register and no data is written in the reception memory buffers.
Reception memory buffer locations are written starting from the address contained in the
ADDRn_RX for a number of bytes corresponding to the received data packet length, CRC
included (i.e. data payload length + 2), or up to the last allocated memory location, as
defined by BL_SIZE and NUM_BLOCK, whichever comes first. In this way, the USB
peripheral never writes beyond the end of the allocated reception memory buffer area. If the
length of the data packet payload (actual number of bytes used by the application) is greater
than the allocated buffer, the USB peripheral detects a buffer overrun condition. in this case,
a STALL handshake is sent instead of the usual ACK to notify the problem to the host, no
interrupt is generated and the transaction is considered failed.
When the transaction is completed correctly, by sending the ACK handshake packet, the
internal COUNT register is copied back in the COUNTn_RX location inside the buffer
description table entry, leaving unaffected BL_SIZE and NUM_BLOCK fields, which
normally do not require to be re-written, and the register is updated in the following way:
DTOG_RX bit is toggled, the endpoint is made invalid by setting STAT_RX = '10' (NAK) and
bit CTR_RX is set. If the transaction has failed due to errors or buffer overrun condition,
none of the previously listed actions take place. The application software must first identify
the endpoint, which is requesting microcontroller attention by examining the EP_ID and DIR
bits in the register. The CTR_RX event is serviced by first determining the transaction type
(SETUP bit in the register); the application software must clear the interrupt flag bit and get
the number of received bytes reading the COUNTn_RX location inside the buffer description
table entry related to the endpoint being processed. After the received data is processed,
the application software should set the STAT_RX bits to '11' (Valid) in the, enabling further
transactions. While the STAT_RX bits are equal to '10' (NAK), any OUT request addressed
to that endpoint is NAKed, indicating a flow control condition: the USB host will retry the
transaction until it succeeds. It is mandatory to execute the sequence of operations in the
above mentioned order to avoid losing the notification of a second OUT transaction
addressed to the same endpoint following immediately the one which triggered the CTR
interrupt.
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