Packet Error Checking - ST STM32F101 Series Reference Manual

Inter-integrated circuit (I2C) interface
Reception using DMA
DMA mode can be enabled for reception by setting the DMAEN bit in the I2C_CR2 register.
The DMAEN bit must be set only after receiving the address sequence, when ADDR is
cleared. Data will be loaded from the I2C_DR register to a Memory area configured using
the DMA peripheral (refer to the DMA specification) whenever a data byte is received. To
map a DMA channel for I
channel number.
When the number of data transfers which has been programmed in the DMA Controller
registers is reached, the DMA controller sends an End of Transfer EOT/ EOT_1 signal to the
2
I C interface and DMA generates an interrupt, if enabled, on the DMA channel interrupt
vector.
Note: Do not enable the ITEVTEN bit in the I2C_CR2 register if DMA is used for reception.
15.4.7

Packet error checking

A PEC calculator has been implemented to improve the reliability of communication. The
PEC is calculated by using a programmable polynomial serially on each bit.
PEC calculation is enabled by setting the ENPEC bit in the I2C_CR1 register. PEC is a
CRC-8 calculated on all message bytes including addresses and R/W bits.
–
–
A PECERR error flag/interrupt is also available in the I2C_SR1 register.
If DMA and PEC calculation are both enabled:-
–
–
To allow intermediate PEC transfers, a control bit is available in the I2C_CR2 register
(LAST bit) to determine if it is really the last DMA transfer or not. If it is the last DMA
request for a master receiver, a NACK is automatically sent after the last received byte.
PEC calculation is corrupted by an arbitration loss.
332/501
2
C reception, perform the following sequence. Here x is the
1. Set the I2C_DR register address in DMA_CPARx register. The data will be
moved from this address to the memory after each RxNE event.
2. Set the memory address in the DMA_CMARx register. The data will be
loaded from the I2C_DR register to this memory area after each RxNE event.
3. Configure the total number of bytes to be transferred in the DMA_CNDTRx
register. After each RxNE event, this value will be decremented.
4. Configure the channel priority using the PL[0:1] bits in the DMA_CCRx
register
5. Reset the DIR bit and configure interrupts in the DMA_CCRx register after
half transfer or full transfer depending on application requirements.
6. Activate the channel by setting the EN bit in the DMA_CCRx register.
In transmission: in the last TxE event: set the PEC transfer bit in the I2C_CR1
register. The PEC will be transferred after the current byte.
In reception: in the last RxNE event: set the PEC bit in the I2C_CR1 register so
that receiver sends a NACK if the next received byte is not equal to the internally
calculated PEC. In case of Master-Receiver, a NACK must follow the PEC
whatever the check result.
In transmission: when the I
controller, it automatically sends a PEC after the last byte.
In reception: when the I
controller, it will automatically consider the next byte as a PEC and will check it. A
DMA request is generated after PEC reception.
2
C interface receives an EOT signal from the DMA
2
C interface receives an EOT_1 signal from the DMA
RM0008