ST STM32F101 Series Reference Manual page 307

RM0008
Receive FIFO mailbox data length control and time stamp register
(CAN_RDTxR) (x=0..1)
Address offsets: 0x1B4, 0x1C4
Reset value: 0xXX where X is undefined
Note: All RX registers are write protected.
31 30 29
r r r
15 14 13
r r r
Bits 31:16 TIME[15:0]: Message Time Stamp
This field contains the 16-bit timer value captured at the SOF detection.
Bits 15:8 FMI[7:0]: Filter Match Index
This register contains the index of the filter the message stored in the mailbox passed through. For
more details on identifier filtering please refer to
Filter Match Index paragraph.
Bits 7:4 Reserved, forced by hardware to 0.
Bits 3:0 DLC[3:0]: Data Length Code
This field defines the number of data bytes a data frame contains (0 to 8). It is 0 in the case of a
remote frame request.
Receive FIFO mailbox data low register (CAN_RDLxR) (x=0..1)
All bits of this register are write protected when the mailbox is not in empty state.
Address offsets: 0x1B8, 0x1C8
Reset value: 0xXX where X is undefined
Note: All RX registers are write protected.
31 30 29
r r r
15 14 13
r r r
Bits 31:24 DATA3[7:0]: Data Byte 3
Data byte 3 of the message.
Bits 23:16 DATA2[7:0]: Data Byte 2
Data byte 2 of the message.
28 27 26 25
r r r r
12 11 10 9
FMI[7:0]
r r r r
28 27 26 25
DATA3[7:0]
r r r r
12 11 10 9
DATA1[7:0]
r r r r
Controller area network (bxCAN)
24 23 22 21
TIME[15:0]
r r r r
8 7 6 5
Reserved
r
Section 14.5.4: Identifier filtering on page 282
24 23 22 21
r r r r
8 7 6 5
r r r r
20 19 18 17
r r r r
4 3 2 1
DLC[3:0]
r r r
20 19 18 17
DATA2[7:0]
r r r r
4 3 2 1
DATA0[7:0]
r r r r
16
r
0
r
-
16
r
0
r
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