Debug Mode; Figure 118. Triggering Timer 1 And 2 With Timer 1 Ti1 Input - ST STM32F101 Series Reference Manual

General purpose timer (TIMx)
counters are aligned, Timer 1 must be configured in Master/Slave mode (slave with respect
to TI1, master with respect to Timer 2):
Configure Timer 1 master mode to send its Enable as trigger output (MMS=001 in the
TIM1_CR2 register).
Configure Timer 1 slave mode to get the input trigger from TI1 (TS=100 in the
TIM1_SMCR register).
Configure Timer 1 in trigger mode (SMS=110 in the TIM1_SMCR register).
Configure the Timer 1 in Master/Slave mode by writing MSM='1' (TIM1_SMCR
register).
Configure Timer 2 to get the input trigger from Timer 1 (TS=001 in the TIM2_SMCR
register).
Configure Timer 2 in trigger mode (SMS=110 in the TIM2_SMCR register).
When a rising edge occurs on TI1 (Timer 1), both counters starts counting synchronously on
the internal clock and both TIF flags are set.
Note: In this example both timers are initialized before starting (by setting their respective UG
bits). Both counters starts from 0, but you can easily insert an offset between them by
writing any of the counter registers (TIMx_CNT). You can see that the master/slave mode
insert a delay between CNT_EN and CK_PSC on timer 1.

Figure 118. Triggering timer 1 and 2 with timer 1 TI1 input.

TIMER1-CEN=CNT_EN
TIMER 1-CK_PSC
TIMER2-CEN=CNT_EN
TIMER 2-CK_PSC
13.4.16

Debug mode

When the microcontroller enters debug mode (Cortex-M3 core - halted), the TIMx counter
either continues to work normally or stops, depending on DBG_TIMx_STOP configuration
bit in DBG module. For more details, refer to
watchdog, bxCAN and I
250/501
CK_INT
TIMER 1-TI1
TIMER1-CNT
TIMER1-TIF
TIMER2-CNT
TIMER2-TIF
2
C.
00 01 02 03 04 05 06 07 08 09
00 01 02 03 04 05 06 07 08 09
Section 20.15.2: Debug support for timers,
RM0008