Control/Status Register (Rcc_Csr) - ST STM32F101 Series Reference Manual

Reset and clock control (RCC)
Bit 1 LSERDY External Low Speed oscillator Ready
Set and reset by hardware to indicate when the external 32 kHz oscillator is stable. This bit needs 6
cycles of external Low Speed oscillator clock to fall down after LSEON reset.
0: External 32 kHz oscillator not ready
1: External 32 kHz oscillator ready
Bit 0 LSEON External Low Speed oscillator enable
Set and reset by software.
0: External 32 kHz oscillator OFF
1: External 32 kHz oscillator ON
4.3.10

Control/status register (RCC_CSR)

Address: 0x24
Reset value: 0x0C00 0000, reset by system Reset, except reset flags by power Reset only.
Access: 0 ≤ wait state ≤ 3, word, half-word and byte access
Wait states are inserted in case of successive accesses to this register.
31 30 29
LPWR WWDG IWDG
RSTF RSTF RSTF RSTF
rw rw rw
15 14 13
Bit 31 LPWRRSTF Low-Power reset flag
Reset by software by writing the RMVF bit.
Set by hardware when a Low-power management reset occurs.
0: No Low-power management reset occurred
1: Low-power management reset occurred
For further information on Low-power management reset, refer to
Reset.
Bit 30 WWDGRSTF Window watchdog reset flag
Reset by software by writing the RMVF bit.
Set by hardware when a window watchdog reset occurs.
0: No window watchdog reset occurred
1: Window watchdog reset occurred
Bit 29 IWDGRSTF Independent Watchdog reset flag
Reset by software by writing the RMVF bit.
Set by hardware when a watchdog reset from V
0: No watchdog reset occurred
1: Watchdog reset occurred
72/501
28 27 26 25
SFT POR PIN
Res.
RSTF RSTF
rw rw rw Res.
12 11 10 9
Reserved
24 23 22
RMVF
rw
8 7 6
Res.
domain occurs.
DD
21 20 19 18
Reserved
Res.
5 4 3 2
Section : Low-power management
RM0008
17 16
1 0
LSI
LSION
RDY
r rw