Power Control Registers; Power Control Register (Pwr_Cr) - ST STM32F101 Series Reference Manual

RM0008
3.4

Power control registers

3.4.1

Power control register (PWR_CR)

Address offset: 0x00
Reset value: 0x0000 0000 (reset by wakeup from Standby mode)
31 30 29
15 14 13
Reserved
Bits 31:9 Reserved, always read as 0.
Bit 8 DBP: Disable Backup Domain write protection.
In reset state, the RTC and backup registers are protected against parasitic write access. This bit
must be set to enable write access to these registers.
0: Access to RTC and Backup registers disabled
1: Access to RTC and Backup registers enabled
Bits 7:5 PLS[2:0]: PVD Level Selection.
These bits are written by software to select the voltage threshold detected by the Power Voltage
Detector
000: 2.2V
001: 2.3V
010: 2.4V
011: 2.5V
100: 2.6V
101: 2.7V
110: 2.8V
111: 2.9V
Note: Refer to the electrical characteristics of the datasheet for more details.
Bit 4 PVDE: Power Voltage Detector Enable.
This bit is set and cleared by software.
0: PVD disabled
1: PVD enabled
Bit 3 CSBF: Clear Standby Flag.
This bit is always read as 0.
0: No effect
1: Clear the SBF Standby Flag (write).
Bit 2 CWUF: Clear Wakeup Flag.
This bit is always read as 0.
0: No effect
1: Clear the WUF Wakeup Flag after 2 System clock cycles. (write)
28 27 26 25
12 11 10 9
Res
24 23 22 21
Reserved
Res.
8 7 6 5
DBP PLS[2:0]
rw rw rw rw
Power control (PWR)
20 19 18 17
4 3 2 1
PVDE CSBF CWUF PDDS
rw rc_w1 rc_w1 rw
16
0
LPDS
rw
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