Data Alignment; Channel-By-Channel Programmable Sample Time; Conversion On External Trigger; Figure 146. Right Alignment Of Data - ST STM32F101 Series Reference Manual

Analog-to-digital converter (ADC)
16.6

Data alignment

ALIGN bit in the ADC_CR2 register selects the alignment of data stored after conversion.
Data can be left or right aligned as shown in
The injected group channels converted data value is decreased by the user-defined offset
written in the ADC_JOFRx registers so the result can be a negative value. The SEXT bit is
the extended sign value.
For regular group channels no offset is subtracted so only twelve bits are significant.

Figure 146. Right alignment of data

Injected group
SEXT SEXT
Regular group
0

Figure 147. Left alignment of data

Injected group
SEXT
Regular group
D11
16.7

Channel-by-channel programmable sample time

ADC samples the input voltage for a number of ADC_CLK cycles which can be modified us-
ing the SMP[2:0] bits in the ADC_SMPR1 and ADC_SMPR2 registers. Each channel can be
sampled with a different sample time.
The total conversion time is calculated as follows:
Tconv = Sampling time + 12.5 cycles
Example:
With an ADCCLK = 14 MHz and a sampling time of 1.5 cycles:
Tconv = 1.5 + 12.5 = 14 cycles = 1µs
16.8

Conversion on external trigger

Conversion can be triggered by an external event (e.g. timer capture, EXTI line). If the EXT-
TRIG control bit is set then external events are able to trigger a conversion. The EXT-
SEL[2:0] and JEXTSEL[2:0] control bits allow the application to select decide which out of 8
possible events can trigger conversion for the regular and injected groups.
Note: When an external trigger is selected for ADC regular or injected conversion, only the rising
edge of the signal can start the conversion.
356/501
SEXT SEXT D11
0 0 0 D11
D11 D10 D9 D8
D10 D9 D8 D7
Figure 146.
D10 D9 D8 D7
D10 D9 D8 D7
D7 D6 D5 D4
D6 D5 D4 D3
and Figure 147.
D6 D5 D4 D3 D2
D6 D5 D4 D3 D2
D3 D2 D1 D0
D2 D1 D0 0
RM0008
D1 D0
D1 D0
0 0 0
0 0 0