Serial Peripheral Interface (Spi); Introduction; Main Features - ST STM32F101 Series Reference Manual

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18

Serial peripheral interface (SPI)

18.1

Introduction

The serial peripheral interface (SPI) allows half/ full-duplex, synchronous, serial
communication with external devices. The interface can be configured as the master and in
this case it provides the communication clock (SCK) to the external slave device. The
interface is also capable of operating in multimaster configuration.
It may be used for a variety of purposes, including Simplex synchronous transfers on 2 lines
with a possible bidirectional data line or reliable communication using CRC checking.
18.2

Main features

Full duplex synchronous transfers on 3 lines
Simplex synchronous transfers on 2 lines with or without a bidirectional data line
8- or 16-bit transfer frame format selection
Master or slave operation
Multimaster mode capability
8 Master mode baud rate prescalers (f
Slave mode frequency (f
Faster communication for both master and slave: Max. SPI speed up to 18 MHz
NSS management by hardware or software for both master and slave: dynamic change
of master/slave operations
Programmable clock polarity and phase
Programmable data order with MSB-first or LSB-first shifting
Dedicated transmission and reception flags with interrupt capability
SPI bus busy status flag
Hardware CRC feature for reliable communication:
–
–
Master mode fault, overrun and CRC error flags with interrupt capability
1-byte transmission and reception buffer with DMA capability: Tx and Rx requests
PCLK
CRC value can be transmitted as last byte in Tx mode
Automatic CRC error checking for last received byte in full duplex mode
/2 max.)
PCLK
/2 max.)
Serial peripheral interface (SPI)
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