Capture/Compare Mode Register 2 (Tim1_Ccmr2) - ST STM32F101 Series Reference Manual

Advanced control timer (TIM1)
12.5.8

Capture/compare mode register 2 (TIM1_CCMR2)

Address offset: 0x1C
Reset value: 0x0000
Refer to the above CCMR1 register description.
15 14 13
OC4
OC4M[2:0]
CE
IC4F[3:0]
rw rw rw
Output Compare mode
Bit 15 OC4CE: Output Compare 4 Clear Enable
Bits 14:12 OC4M: Output Compare 4 Mode.
Bit 11 OC4PE: Output Compare 4 Preload enable.
Bit 10 OC4FE: Output Compare 4 Fast enable.
Bits 9:8 CC4S: Capture/Compare 4 Selection.
This bit-field defines the direction of the channel (input/output) as well as the used input.
00: CC4 channel is configured as output.
01: CC4 channel is configured as input, IC4 is mapped on TI4.
10: CC4 channel is configured as input, IC4 is mapped on TI3.
11: CC4 channel is configured as input, IC4 is mapped on TRC. This mode is working only if an
internal trigger input is selected through TS bit (TIM1_SMCR register)
Note: CC4S bits are writable only when the channel is OFF (CC4E = '0' in TIM1_CCER).
Bit 7 OC3CE: Output Compare 3 Clear Enable
Bits 6:4 OC3M: Output Compare 3 Mode.
Bit 3 OC3PE: Output Compare 3 Preload enable.
Bit 2 OC3FE: Output Compare 3 Fast enable.
Bits 1:0 CC3S: Capture/Compare 3 Selection.
This bit-field defines the direction of the channel (input/output) as well as the used input.
00: CC3 channel is configured as output.
01: CC3 channel is configured as input, IC3 is mapped on TI3.
10: CC3 channel is configured as input, IC3 is mapped on TI4.
11: CC3 channel is configured as input, IC3 is mapped on TRC. This mode is working only if an
internal trigger input is selected through TS bit (TIM1_SMCR register)
Note: CC3S bits are writable only when the channel is OFF (CC3E = '0' in TIM1_CCER).
202/501
12 11 10 9
OC4 OC4
PE FE
CC4S[1:0]
IC4PSC[1:0]
rw rw rw rw
8 7 6 5
OC3
OC3M[2:0]
CE.
IC3F[3:0]
rw rw rw rw
4 3 2 1
OC3 OC3
PE FE
CC3S[1:0]
IC3PSC[1:0]
rw rw rw rw
RM0008
0
rw