Afio Register Description; Event Control Register (Afio_Evcr); Table 24. Spi1 Remapping - ST STM32F101 Series Reference Manual

General-purpose and alternate-function I/Os (GPIOs and AFIOs)
Table 24.
5.4

AFIO register description

Refer to
5.4.1

Event control register (AFIO_EVCR)

Address offset: 0x00
Reset value: 0x0000 0000
31 30 29
15 14 13
Bits 31:8 Reserved
Bit 7 EVOE Event Output Enable
Set and cleared by software. When set the EVENTOUT Cortex output is connected to the I/O
selected by the PORT[2:0] and PIN[3:0] bits.
Bits 6:4 PORT[2:0]: Port selection
Set and cleared by software. Select the port used to output the Cortex EVENTOUT signal.
000: PA selected
001: PB selected
010: PC selected
011: PD selected
100: PE selected
Bits 3:0 PIN[3:0] Pin selection (x = A .. E)
Set and cleared by software. Select the pin used to output the Cortex EVENTOUT signal.
0000: Px0 selected
0001: Px1 selected
0010: Px2 selected
0011: Px3 selected
...
1111: Px15 selected
92/501
SPI1 remapping
Alternate function
SPI1_NSS
SPI1_SCK
SPI1_MISO
SPI1_MOSI
Section 1.1 on page 23
28 27 26 25
12 11 10 9
Reserved
SPI1_REMAP = 0
PA4
PA5
PA6
PA7
for a list of abbreviations used in register descriptions.
24 23 22
Reserved
8 7 6
EVOE PORT[2:0]
rw rw
SPI1_REMAP = 1
PA15
21 20 19 18
5 4 3 2
PIN[3:0]
rw rw rw rw
RM0008
PB3
PB4
PB5
17 16
1 0
rw rw