Apb2 Peripheral Reset Register (Rcc_Apb2Rstr) - ST STM32F101 Series Reference Manual

Reset and clock control (RCC)
4.3.4

APB2 Peripheral reset register (RCC_APB2RSTR)

Address offset: 0x0C
Reset value: 0x00000 0000
Access: no wait state, word, half-word and byte access
31 30 29
15 14 13
USART
SPI1
Res. 1 Res.
RST
RST
Res. rw Res.
Bits 31:15 Reserved, always read as 0.
Bit 14 USART1RST USART1 reset
Set and reset by software.
0: No effect
1: Reset USART1
Bit 13 Reserved, always read as 0.
Bit 12 SPI1RST SPI 1 reset
Set and reset by software.
0: No effect
1: Reset SPI 1
Bit 11 TIM1RST TIM1 Timer reset
Set and reset by software.
0: No effect
1: Reset TIM1 timer
Bit 10 ADC2RST ADC 2 interface reset
Set and reset by software.
0: No effect
1: Reset ADC 2 interface
Bit 9 ADC1RST ADC 1 interface reset
Set and reset by software.
0: No effect
1: Reset ADC 1 interface
Bits 8:7 Reserved, always read as 0.
Bit 6 IOPERST IO port E reset
Set and reset by software.
0: No effect
1: Reset IO port E
62/501
28 27 26 25
12 11 10 9
TIM1 ADC2 ADC1
RST RST RST
rw rw rw rw
24 23 22 21
Reserved
Res.
8 7 6 5
IOPE IOPD
Reserved
RST RST
Res. rw rw
20 19 18 17
4 3 2 1
IOPC IOPB IOPA
Res.
RST RST RST
rw rw rw Res.
RM0008
16
0
AFIO
RST
rw