Block Diagram; Figure 165. Usart Block Diagram - ST STM32F101 Series Reference Manual

RM0008
19.3.1

Block diagram

Figure 165. USART block diagram

TX
RX
IrDA
SIR
SW_RX
ENDEC
BLOCK
IRDA_OUT
IRDA_IN
nRTS
Hardware
flow
nCTS
controller
USARTDIV = DIV_Mantissa + (DIV_Fraction / 16)
Universal synchronous asynchronous receiver transmitter (USART)
PWDATA
Write
(CPU or DMA)
Transmit Data Register (TDR)
Transmit Shift Register
CR3
DMAT DMAR SCEN NACK
CR2
USART Address
TRANSMIT
CONTROL
CR1
RXNE IDLE
TXEIE TCIE TE
IE
IE
USART
INTERRUPT
CONTROL
TRANSMITTER
CLOCK
/16
f
PCLKx(x=1,2)
Read
(CPU or DMA)
Receive Data Register (RDR)
Receive Shift Register
GTPR
GT PSC
CR2
HD
IRLP IREN
LINE
M
UE
WAKE
UP
UNIT
RE RWU SBK CTS LBD
USART_BRR
TRANSMITTER RATE
TE
CONTROL
/
USARTDIV
DIV_Mantissa
15
RECEIVER RATE
RE CONTROL
CONVENTIONAL BAUD RATE GENERATOR
PRDATA
(DATA REGISTER) DR
SCLK CONTROL
STOP[1:0] CKEN CPOL CPHA LBCL
CR1
WAKE PCE PS PEIE
RECEIVER
CLOCK
RECEIVER
CONTROL
SR
TXE TC RXNE IDLE ORE NE FE
DIV_Fraction
4 0
SCLK
PE
433/501