Figure 95. Control Circuit In External Clock Mode 1; Figure 96. External Trigger Input Block - ST STM32F101 Series Reference Manual

RM0008
The delay between the rising edge on TI2 and the actual clock of the counter is due to the
resynchronization circuit on TI2 input.

Figure 95. Control circuit in external clock mode 1

External clock source mode 2
This mode is selected by writing ECE=1 in the TIMx_SMCR register.
The counter can count at each rising or falling edge on the external trigger input ETR.
The Figure 96

Figure 96. External trigger input block

ETR pin
For example, to configure the upcounter to count each 2 rising edges on ETR, use the
following procedure:
1. As no filter is needed in this example, write ETF[3:0]=0000 in the TIMx_SMCR register.
2. Set the prescaler by writing ETPS[1:0]=01 in the TIMx_SMCR register
3. Select rising edge detection on the ETR pin by writing ETP=0 in the TIMx_SMCR
register
4. Enable external clock mode 2 by writing ECE=1 in the TIMx_SMCR register.
5. Enable the counter by writing CEN=1 in the TIMx_CR1 register.
The counter counts once each 2 ETR rising edges.
The delay between the rising edge on ETR and the actual clock of the counter is due to the
resynchronization circuit on the ETRP signal.
CNT_EN
Counter clock = CK_CNT = CK_PSC
Counter register
gives an overview of the external trigger input block.
ETR
0
divider
/1, /2, /4, /8
1
ETP ETPS[1:0]
TIMx_SMCR
TIMx_SMCR
TI2
34
TIF
Write TIF=0
ETRP
filter
downcounter
CK_INT
ETF[3:0]
TIMx_SMCR
General purpose timer (TIMx)
35 36
TI2F or
or
TI1F or
encoder
mode
external clock
TRGI
mode 1
ETRF external clock
mode 2
CK_INT
internal clock
mode
(internal clock)
ECE SMS[2:0]
TIMx_SMCR
CK_PSC
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