Voltage Regulator; Power Supply Supervisor; Power On Reset (Por)/Power Down Reset (Pdr); Programmable Voltage Detector (Pvd) - ST STM32F101 Series Reference Manual

RM0008
3.1.3

Voltage regulator

The voltage regulator is always enabled after Reset. It works in three different modes
depending on the application modes.
In Run mode, the regulator supplies full power to the 1.8 V domain (core, memories
and digital peripherals).
In Stop mode the regulator supplies low-power to the 1.8 V domain, preserving
contents of registers and SRAM
In Standby Mode, the regulator is powered off. The contents of the registers and SRAM
are lost except for the Standby circuitry and the Backup Domain.
3.2

Power supply supervisor

3.2.1

Power on reset (POR)/power down reset (PDR)

The device has an integrated POR/PDR circuitry that allows proper operation starting
from/down to 2 V.
The device remains in Reset mode when V
without the need for an external reset circuit. For more details concerning the power
on/power down reset threshold, refer to the electrical characteristics of the datasheet.
Figure 4.
Reset
3.2.2

Programmable voltage detector (PVD)

You can use the PVD to monitor the V
selected by the PLS[2:0] bits in the
The PVD is enabled by setting the PVDE bit.
A PVDO flag is available, in the
is higher or lower than the PVD threshold. This event is internally connected to the EXTI
line16 and can generate an interrupt if enabled through the EXTI registers. The PVD output
interrupt can be generated when V
Power on reset/power down reset waveform
V
DD
POR
Power control/status register
is below a specified threshold, V
DD
40 mV
hysteresis
Temporization
t
RSTTEMPO
power supply by comparing it to a threshold
DD
Power control register
drops below the PVD threshold and/or when V
DD
Power control (PWR)
POR/PDR
PDR
(PWR_CR).
(PWR_CSR), to indicate if V
,
DD
DD
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