Figure 126. Receive Fifo States - ST STM32F101 Series Reference Manual

RM0008
managed completely by hardware. The application accesses the messages stored in the
FIFO through the FIFO output mailbox.
Valid message
A received message is considered as valid when it has been received correctly according to
the CAN protocol (no error until the last but one bit of the EOF field) and It passed through
the identifier filtering successfully, see

Figure 126. Receive FIFO states

FIFO management
Starting from the empty state, the first valid message received is stored in the FIFO which
becomes pending_1. The hardware signals the event setting the FMP[1:0] bits in the CRFR
register to the value 01b. The message is available in the FIFO output mailbox. The software
reads out the mailbox content and releases it by setting the RFOM bit in the CRFR register.
The FIFO becomes empty again. If a new valid message has been received in the
meantime, the FIFO stays in pending_1 state and the new message is available in the
output mailbox.
If the application does not release the mailbox, the next valid message will be stored in the
FIFO which enters pending_2 state (FMP[1:0] = 10b). The storage process is repeated for
the next valid message putting the FIFO into pending_3 state (FMP[1:0] = 11b). At this
point, the software must release the output mailbox by setting the RFOM bit, so that a
EMPTY
Valid Message
FMP=0x00
FOVR=0
Received
Release
Mailbox
Section 14.5.4: Identifier
PENDING_1
FMP=0x01
FOVR=0
Valid Message
Release
Received
Mailbox
RFOM=1
PENDING_2
FMP=0x10
FOVR=0
Valid Message
Release
Mailbox
Received
RFOM=1
PENDING_3
Valid Message
FMP=0x11
FOVR=0
Release
Mailbox
RFOM=1
Controller area network (bxCAN)
filtering.
Received
OVERRUN
FMP=0x11
FOVR=1
Valid Message
Received
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