Figure 33. Counter Timing Diagram, Update Event When Arpe=1 (Tim1_Arr Preloaded) - ST STM32F101 Series Reference Manual

Advanced control timer (TIM1)
Figure 33. Counter timing diagram, update event when ARPE=1 (TIM1_ARR
Downcounting mode
In downcounting mode, the counter counts from the auto-reload value (content of the
TIM1_ARR register) down to 0, then restarts from the auto-reload value and generates a
counter underflow event.
If the repetition counter is used, the update event (UEV) is generated after downcounting is
repeated for the number of times programmed in the repetition counter register
(TIM1_RCR). Else the update event is generated at each counter underflow.
Setting the UG bit in the TIM1_EGR register (by software or by using the slave mode
controller) also generates an update event.
The UEV update event can be disabled by software by setting the UDIS bit in TIM1_CR1
register. This is to avoid updating the shadow registers while writing new values in the
preload registers. Then no update event occurs until UDIS bit has been written to 0.
However, the counter restarts from the current auto-reload value, whereas the counter of the
prescaler restarts from 0 (but the prescale rate doesn't change).
In addition, if the URS bit (update request selection) in TIM1_CR1 register is set, setting the
UG bit generates an update event UEV but without setting the UIF flag (thus no interrupt or
DMA request is sent). This is to avoid generating both update and capture interrupts when
clearing the counter on the capture event.
When an update event occurs, all the registers are updated and the update flag (UIF bit in
TIM1_SR register) is set (depending on the URS bit):
The repetition counter is reloaded with the content of TIM1_RCR register
The auto-reload active register is updated with the preload value (content of the
TIM1_ARR register). Note that the auto-reload is updated before the counter is
reloaded, so that the next period is the expected one
The following figures show some examples of the counter behavior for different clock
frequencies when TIM1_ARR=0x36.
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preloaded)
CK_PSC
CNT_EN
Timer clock = CK_CNT
Counter register
Counter overflow
Update event (UEV)
Update interrupt flag (UIF)
Auto-reload preload register
Auto-reload shadow register
Write a new value in TIM1_ARR
F0 F1 F2 F3 F4 F5 00 01 02 03 04 05 06 07
F5
F5
RM0008
36
36