RM0008
Figure 135. I
SDA
SCL
SMBALERT
Note: SMBALERT is an optional signal in SMBus mode. This signal is not applicable if
SMBus is disabled.
2
C block diagram
DATA
CONTROL
CLOCK
CONTROL
CLOCK CONTROL
REGISTER (CCR)
CONTROL REGISTERS
(CR1&CR2)
STATUS REGISTERS
(SR1&SR2)
Inter-integrated circuit (I2C) interface
DATA REGISTER
DATA SHIFT REGISTER
COMPARATOR
OWN ADDRESS REGISTER
DUAL ADDRESS REGISTER
PEC REGISTER
CONTROL
LOGIC
INTERRUPTS
DMA REQUESTS & ACK
PEC CALCULATION
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