Endpoint-Specific Registers - ST STM32F101 Series Reference Manual

USB full speed device interface (USB)
17.6.2

Endpoint-specific registers

The number of these registers varies according to the number of endpoints that the USB
peripheral is designed to handle. The USB peripheral supports up to 8 bidirectional
endpoints. Each USB device must support a control endpoint whose address (EA bits) must
be set to 0. The USB peripheral behaves in an undefined way if multiple endpoints are
enabled having the same endpoint number value. For each endpoint, an register is available
to store the endpoint specific information.
USB endpoint n register (), n=[0..7]
Address offset: 0x00 to 0x1C
Reset value: 0x0000
15 14 13
CTR_ DTOG
STAT__X[1:0]
RX _RX
r-c t t
They are also reset when an USB reset is received from the USB bus or forced through bit
FRES in the CTLR register, except the CTR_RX and CTR_TX bits, which are kept
unchanged to avoid missing a correct packet notification immediately followed by an USB
reset event. Each endpoint has its register where n is the endpoint identifier.
Read-modify-write cycles on these registers should be avoided because between the read
and the write operations some bits could be set by the hardware and the next write would
modify them before the CPU has the time to detect the change. For this purpose, all bits
affected by this problem have an 'invariant' value that must be used whenever their
modification is not required. It is recommended to modify these registers with a load
instruction where all the bits, which can be modified only by the hardware, are written with
their 'invariant' value.
Bit 15 CTR_RX: Correct Transfer for reception
This bit is set by the hardware when an OUT/SETUP transaction is successfully completed on this
endpoint; the software can only clear this bit. If the CTRM bit in register is set accordingly, a generic
interrupt condition is generated together with the endpoint related interrupt condition, which is
always activated. The type of occurred transaction, OUT or SETUP, can be determined from the
SETUP bit described below.
A transaction ended with a NAK or STALL handshake does not set this bit, since no data is actually
transferred, as in the case of protocol errors or data toggle mismatches.
This bit is read/write but only '0' can be written, writing 1 has no effect.
404/501
12 11 10 9
EP
SETUP
TYPE[1:0]
t r rw rw
8 7 6 5
EP_ CTR_ DTOG_
STAT_TX[1:0]
KIND TX TX
rw r-c t t
RM0008
4 3 2 1
EA[3:0]
t rw rw rw
0
rw