ST STM32F101 Series Reference Manual page 255

RM0008
Bits 11:8 ETF[3:0]: External Trigger Filter.
This bit-field then defines the frequency used to sample ETRP signal and the length of the digital filter
applied to ETRP. The digital filter is made of an event counter in which N events are needed to
validate a transition on the output:
0000: No filter, sampling is done at f
0001: f
SAMPLING
0010: f
SAMPLING
0011: f
SAMPLING
0100: f
SAMPLING
0101: f
SAMPLING
0110: f
SAMPLING
0111: f
SAMPLING
1000: f
SAMPLING
1001: f
SAMPLING
1010: f
SAMPLING
1011: f
SAMPLING
1100: f
SAMPLING
1101: f
SAMPLING
1110: f
SAMPLING
1111: f
SAMPLING
Bit 7 MSM: Master/Slave mode.
0: No action
1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization
between the current timer and its slaves (through TRGO). It is useful if we want to synchronize
several timers on a single external event.
Bits 6:4 TS: Trigger Selection.
This bit-field selects the trigger input to be used to synchronize the counter.
000: Internal Trigger 0 (ITR0). TIM1
001: Internal Trigger 1 (ITR1). TIM2
010: Internal Trigger 2 (ITR2). TIM3
011: Internal Trigger 3 (ITR3). TIM4
100: TI1 Edge Detector (TI1F_ED).
101: Filtered Timer Input 1 (TI1FP1).
110: Filtered Timer Input 2 (TI2FP2).
111: External Trigger input (ETRF).
Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong
edge detections at the transition.
Bit 3 Reserved, always read as 0.
.
DTS
=f , N=2.
CK_INT
=f , N=4.
CK_INT
=f , N=8.
CK_INT
=f /2, N=6.
DTS
=f /2, N=8.
DTS
=f /4, N=6.
DTS
=f /4, N=8.
DTS
=f /8, N=6.
DTS
=f /8, N=8.
DTS
=f /16, N=5.
DTS
=f /16, N=6.
DTS
=f /16, N=8.
DTS
=f /32, N=5.
DTS
=f /32, N=6.
DTS
=f /32, N=8.
DTS
General purpose timer (TIMx)
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