Repetition Downcounter; Figure 44. Counter Timing Diagram, Update Event With Arpe=1 (Counter Overflow) - ST STM32F101 Series Reference Manual

RM0008

Figure 44. Counter timing diagram, Update event with ARPE=1 (counter overflow)

12.4.3

Repetition downcounter

Section 12.4.1: Time base unit
respect to the counter overflows/underflows. It is actually generated only when the repetition
downcounter has reached zero. This can be useful when generating PWM signals.
This means that data are transferred from the preload registers to the shadow registers
(TIM1_ARR auto-reload register, TIM1_PSC prescaler register, but also TIM1_CCRx
capture/compare registers in compare mode) every N counter overflows or underflows,
where N is the value in the TIM1_RCR repetition counter register.
The repetition downcounter is decremented:
At each counter overflow in upcounting mode,
At each counter underflow in downcounting mode,
At each counter overflow and at each counter underflow in center-aligned mode.
Although this limits the maximum number of repetition to 128 PWM cycles, it makes it
possible to update the duty cycle twice per PWM period. When refreshing compare
registers only once per PWM period in center-aligned mode, maximum resolution is
2xT
The repetition downcounter is an auto-reload type; the repetition rate is maintained as
defined by the TIM1_RCR register value (refer to
generated by software (by setting the UG bit in TIM1_EGR register) or by hardware through
the slave mode controller, it occurs immediately whatever the value of the repetition
downcounter is and the repetition downcounter is reloaded with the content of the
TIM1_RCR register.
CK_PSC
Timer clock = CK_CNT
Counter register
Counter overflow
Update event (UEV)
Update interrupt flag (UIF)
Auto-reload preload register
Write a new value in TIM1_ARR
Auto-reload active register
, due to the symmetry of the pattern.
ck
CNT_EN
F7 F8 F9 FA FB FC
FD
FD
describes how the update event (UEV) is generated with
Figure
Advanced control timer (TIM1)
36 35 34 33 32 31 30 2F
36
36
45). When the update event is
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