ST STM32F101 Series Reference Manual page 174

Advanced control timer (TIM1)
When a break occurs (selected level on the break input):
The MOE bit is cleared asynchronously, putting the outputs in inactive state, idle state
or in reset state (selected by the OSSI bit). This feature functions even if the MCU
oscillator is off.
Each output channel is driven with the level programmed in the OISx bit in the
TIM1_CR2 register as soon as MOE=0. If OSSI=0 then the timer releases the enable
output else the enable output remains high.
When complementary outputs are used:
–
–
–
The break status flag (BIF bit in the TIM1_SR register) is set. An interrupt can be
generated if the BIE bit in the TIM1_DIER register is set. A DMA request can be sent if
the BDE bit in the TIM1_DIER register is set.
If the AOE bit in the TIM1_BDTR register is set, the MOE bit is automatically set again
at the next update event UEV. This can be used to perform a regulation, for instance.
Else, MOE remains low until you write it to '1' again. In this case, it can be used for
security and you can connect the break input to an alarm from power drivers, thermal
sensors or any security components.
Note: The break inputs is acting on level. Thus, the MOE cannot be set while the break input is
active (neither automatically nor by software). In the meantime, the status flag BIF cannot be
cleared.
The break can be generated by the BRK input which has a programmable polarity and an
enable bit BKE in the TIM1_BDTR Register.
In addition to the break input and the output management, a write protection has been
implemented inside the break circuit to safeguard the application. It allows you to freeze the
configuration of several parameters (dead-time duration, OCx/OCxN polarities and state
when disabled, OCxM configurations, break enable and polarity). You can choose from 3
levels of protection selected by the LOCK bits in the TIM1_BDTR register. Refer to
Section 12.5.18: Break and dead-time register (TIM1_BDTR) on page
can be written only once after an MCU reset.
The Figure 62
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The outputs are first put in reset state inactive state (depending on the polarity).
This is done asynchronously so that it works even if no clock is provided to the
timer.
If the timer clock is still present, then the dead-time generator is reactivated in
order to drive the outputs with the level programmed in the OISx and OISxN bits
after a dead-time. Even in this case, OCx and OCxN cannot be driven to their
active level together. Note that because of the resynchronization on MOE, the
dead-time duration is a bit longer than usual (around 2 ck_tim clock cycles).
If OSSI=0 then the timer releases the enable outputs else the enable outputs
remain or become high as soon as one of the CCxE or CCxNE bits is high.
shows an example of behavior of the outputs in response to a break.
RM0008
209. The LOCK bits