Debug support (DBG)
DBGMCU_CR
Address: 0xE0042004
Only 32-bit access supported
POR Reset: 0x00000000 (not reset by system reset)
31
30
29
28
15
14
13
12
DBG_I2C
DBG_
DBG_
DBG_
1_SMBU
CAN_
TIM4_
TIM3_
S_TIME
STOP
STOP
STOP
OUT
rw
rw
rw
rw
Bits 31:15 Reserved, must be kept cleared.
Bit 16 DBG_I2C2_SMBUS_TIMEOUT SMBUS timeout mode stopped when Core is halted
0: Same behavior as in normal mode.
1: The SMBUS timeout is frozen
Bit 15 DBG_I2C1_SMBUS_TIMEOUT SMBUS timeout mode stopped when Core is halted
0: Same behavior as in normal mode.
1: The SMBUS timeout is frozen.
Bit 14 DBG_CAN_STOP: Debug CAN stopped when Core is halted
0: Same behavior as in normal mode.
1: The CAN receive registers are frozen.
Bits 13:10 DBG_TIMx_STOP: Regular data. x=4..1
0: The clock of the involved Timer Counter is fed even if the core is halted.
1: The clock of the involved Timer counter is stopped when the core is halted.
Bit 9 DBG_WWDG_STOP: Debug Window Watchdog stopped when Core is halted
0: The Window Watchdog Counter clock continues even if the core is halted.
1: The Window Watchdog Counter clock is stopped when the core is halted.
Bit 8 DBG_IWDG_STOP: Debug Independent Watchdog stopped when Core is halted
0: The Watchdog counter clock continues even if the core is halted.
1: The Watchdog counter clock is stopped when the core is halted.
Bits 7:5 TRACE_MODE[1:0] and TRACE_IOEN: Trace Pin Assignment Control
– With TRACE_IOEN=0:
TRACE_MODE=xx: TRACE pins not assigned (default state)
– With TRACE_IOEN=1:
TRACE_MODE=00: TRACE pin assignment for Asynchronous Mode
TRACE_MODE=01: TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 1
TRACE_MODE=10: TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 2
TRACE_MODE=11: TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 4
Bit 4:3 Reserved, must be kept cleared.
486/501
27
26
25
24
Reserved
Res.
11
10
9
8
DBG_
DBG_
DBG_
DBG_
TIM2_
TIM1_
WWDG_
IWDG
STOP
STOP
STOP
STOP
rw
rw
rw
rw
23
22
21
20
7
6
5
4
TRACE_
TRACE_
MODE
Reserved
IOEN
[1:0]
rw
rw
rw
RM0008
19
18
17
3
2
1
DBG_
DBG_
STANDB
STOP
Y
Res.
rw
rw
16
DBG_I2C
2_SMBU
S_TIMEO
UT
rw
0
DBG_
SLEEP
rw
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