Timer Alternate Function Remapping; Table 15. Debug Port Mapping; Table 16. Timer 4 Alternate Function Remapping - ST STM32F101 Series Reference Manual

RM0008
Table 14.
To optimize the number of free GPIOs during debugging, this mapping can be configured in
different ways by programming the SWJ_CFG[1:0] bits in the
configuration register
Table 15.
SWJ
_CFG
[2:0]
000
001
010
100
Other Forbidden
1. Released only if not using asynchronous trace.
5.3.5

Timer alternate function remapping

Timer 4 channels 1 to 4 can be remapped from Port B to Port D.
Other timer remapping possibilities are listed in
Refer to
Table 16.
General-purpose and alternate-function I/Os (GPIOs and AFIOs)
Debug interface signals (continued)
Alternate function
JTDI
JTDO / TRACESWO
JNTRST
TRACECK
TRACED0
TRACED1
TRACED2
TRACED3
(AFIO_MAPR). Refer to
Debug port mapping
Available debug ports
Full SWJ (JTAG-DP + SW-DP)
(Reset state)
Full SWJ (JTAG-DP + SW-DP)
but without JNTRST
JTAG-DP Disabled and
SW-DP Enabled
JTAG-DP Disabled and
SW-DP Disabled
AF remap and debug I/O configuration register
Timer 4 alternate function remapping
Alternate function
TIM4_CH1
TIM4_CH2
GPIO port
PA15
PB3
PB4
PE2
PE3
PE4
PE5
PE6
AF remap and debug I/O
Table 15
SWJ I/O pin assigned
PA.13 / PA.14 /
PA.15 /
JTMS/ JTCK/S
JTDI
SWDIO WCLK
X X
X X
X X
free free
Table 17 to Table
(AFIO_MAPR).
TIM4_REMAP = 0
PB6
PB7
PB.3 /
JTDO/ PB.4/
TRACE JNTRST
SWO
X X
X x
(1)
free free
free free
19.
TIM4_REMAP = 1
PD12
PD13
X
free
free
free
(1)
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