ST STM32F101 Series Reference Manual page 302

Controller area network (bxCAN)
CAN bit timing register (CAN_BTR)
Address offset: 0x1C
Reset value: 0x0123 0000
Note: This register can only be accessed by the software when the CAN hardware is in
initialization mode.
31 30 29
SILM LBKM
rw rw
15 14 13
Reserved Reserved
rw
Bit 31 SILM: Silent Mode (Debug)
0: Normal operation
1: Silent Mode
Bit 30 LBKM: Loop Back Mode (Debug)
0: Loop Back Mode disabled
1: Loop Back Mode enabled
Bits 29:26 Reserved, forced by hardware to 0.
Bits 25:24 SJW[1:0]: Resynchronization Jump Width
These bits define the maximum number of time quanta the CAN hardware is allowed to lengthen or
shorten a bit to perform the resynchronization.
t = t
RJW
Bit 23 Reserved, forced by hardware to 0.
Bits 22:20 TS2[2:0]: Time Segment 2
These bits define the number of time quanta in Time Segment 2.
t = t
BS2
Bits 19:16 TS1[3:0]: Time Segment 1
These bits define the number of time quanta in Time Segment 1
t = t
BS1
For more information on bit timing, please refer to
Bits 15:10 Reserved, forced by hardware to 0.
Bits 9:0 BRP[9:0]: Baud Rate Prescaler
These bits define the length of a time quanta.
t = (BRP[9:0]+1) x t
q
302/501
28 27 26 25
Reserved
rw
12 11 10 9
rw
x (SJW[1:0] + 1)
CAN
x (TS2[2:0] + 1)
CAN
x (TS1[3:0] + 1)
CAN
PCLK
24 23 22
SJW[1:0] Res.
rw rw
8 7 6
rw rw rw
Section 14.5.7: Bit timing on page
21 20 19 18
TS2[2:0]
rw rw rw rw
5 4 3
BRP[9:0]
rw rw rw rw
RM0008
17 16
TS1[3:0]
rw rw
2 1 0
rw rw
288.