Internal Pull-Up And Pull-Down On Jtag Pins; Table 72. Flexible Swj-Dp Pin Assignment - ST STM32F101 Series Reference Manual

Debug support (DBG)
Table 72.
SWJ_
CFG
[2:0]
Full SWJ (JTAG-DP + SW-DP) - Reset
000
State
Full SWJ (JTAG-DP + SW-DP) but without
001
JNTRST
010 JTAG-DP Disabled and SW-DP Enabled
100 JTAG-DP Disabled and SW-DP Disabled
other Forbidden
Note: When the APB bridge write buffer is full, it takes one extra APB cycle when writing the
REMAP_AF register. This is because the deactivation of the JTAGSW pins is done in two
cycles to guarantee a clean level on the nTRST and TCK input signals of the core.
Cycle 1: the JTAGSW input signals to the core are tied to 1 or 0 (to 1 for nTRST, TDI
and TMS, to 0 for TCK)
Cycle 2: the GPI/O controller takes the control signals of the SWJTAG I/O pins (like
controls of direction, pull-up/down, Schmitt trigger activation, etc.).
20.4.3

Internal pull-up and pull-down on JTAG pins

It is necessary to ensure that the JTAG input pins are not floating since they are directly
connected to flip-flops to control the debug mode features. Special care must be taken with
the SWCLK/TCK pin which is directly connected to the clock of some of these flip-flops.
To avoid any uncontrolled I/O levels, the STM32F10xxx embeds internal pull-ups and pull-
downs on JTAG input pins:
JNTRST: Internal pull-up
JTDI: Internal pull-up
JTMS/SWDIO: Internal pull-up
TCK/SWCLK: Internal pull-down
Once a JTAG I/O is released by the user software, the GPIO controller takes control again.
The reset states of the GPIO control registers put the I/Os in the equivalent state:
JNTRST: Input pull-up
JTDI: Input pull-up
JTMS/SWDIO: Input pull-up
JTCK/SWCLK: Input pull-down
JTDO: Input floating
The software can then use these I/Os as standard GPIOs.
Note: The JTAG IEEE standard recommends to add pull-ups on TDI, TMS and nTRST but there is
no special recommendation for TCK. However, for STM32F10xxx, an integrated pull-down is
used for JTCK.
Having embedded pull-ups and pull-downs removes the need to add external resistors.
472/501
Flexible SWJ-DP pin assignment
Available debug ports
SWJ I/O pin assigned
PA13 / PA14 /
PA15 /
JTMS/ JTCK/
JTDI
SWDIO SWCLK
X X X
X X X
X X
Released
RM0008
PB3 / PB4/
JTDO JNTRST
X X
X