Spi Status Register (Spi_Sr) - ST STM32F101 Series Reference Manual

Serial peripheral interface (SPI)
18.4.3

SPI status register (SPI_SR)

Address offset: 0x08
Reset value: 0000 0010 (0x0002)
15 14 13
Bits 15:8 Reserved. Forced to 0 by hardware.
Bit 7 BSY: Busy flag
0: SPI not busy
1: SPI is busy in communication or Tx buffer is not empty
This flag is set and reset by hardware.
Bit 6 OVR: Overrun flag
0: No Overrun occurred
1: Overrun occurred
This flag is set by hardware and reset by a software sequence. Refer to
for software sequence.
Bit 5 MODF: Mode fault
0: No Mode fault occurred
1: Mode fault occurred
This flag is set by hardware and reset by a software sequence. Refer to
for software sequence.
Bit 4 CRCERR: CRC error flag
0: CRC value received matches the SPI_RXCRCR value
1: CRC value received does not match the SPI_RXCRCR value
This flag is set by hardware and cleared by software writing 0.
Note:
This bit has a meaning in full-duplex mode only.
Bit 3:2 Reserved. Forced to 0 by hardware.
Bit 1 TXE: Transmit buffer empty
0: Tx buffer not empty
1: Tx buffer empty
Bit 0 RXNE: Receive buffer not empty
0: Rx buffer empty
1: Rx buffer not empty
426/501
12 11 10 9
Reserved
8 7 6 5
BSY OVR MODF
r rc rc
4 3 2 1
CRC
Reserved TXE
ERR
rc r
Section 18.3.8 on page 422
Section 18.3.8 on page 422
RM0008
0
RXNE
r