ST STM32F101 Series Reference Manual page 497

RM0008
Table 87.
Date
19-Oct-2007
continued
Document revision history (continued)
Revision
Figure 87: Counter timing diagram, internal clock divided by 1,
TIMx_ARR=0x6
modified.
CKD definition modified in
Bit 8 and Bit 9 added to
(BKP_RTCCR).
Bit 15 and Bit 16 added to
debug mode on page 334
Stop and Standby modified in
Table 6: Sleep-on-exit
HSITRIM[4:0] bit description modified in
register (RCC_CR). Note modified in MCO description in
Clock configuration register
RCC_CR row modified in
Bits 15:0 description modified in
(GPIOx_BRR)
Figure 9, Figure
Section 2.3.4: Embedded Flash memory on page 29
REV_ID bit description added to
Reset value modified in
and HSITRIM[4:0] description modified.
Section 5.1.1 on page 78
GPIO register description on page
modified in
1
Clock control register (RCC_CR)
continued
Note added in ASOS and ASOE bit descriptions in
Section 20.15.2: Debug support for timers, watchdog, bxCAN and I2C
modified. Table 86: DBG - register map and reset values
Section 17.6.3: Buffer descriptor table
Center-aligned mode (up/down counting) on page 156
mode (up/down counting) on page 222
Figure 58: Center-aligned PWM waveforms (ARR=8) on page 171
Figure 104: Center-aligned PWM waveforms (ARR=8) on page 235
modified.
RSTCAL description modified in
(ADC_CR2).
Note changed below
input clock). Note added below
ADC conversion time modified in
Auto-injection on page 353
Note added in
interleaved. Note added to
as GPIO ports
changed from 32 to 40 kHz.
kHz input clock)
Memory map
organization modified in
External event that trigger ADC conversion is EXTI line instead of external
interrupt (see
Appendix A: Important notes on page 495
Changes
and Figure 102: Output compare mode, toggle on OC1.
Section 13.5.1: Control register 1
Section 9.5.2: RTC clock calibration register
DBGMCU_CR on page
added.
Table 4: Low-power mode
modified. Debug mode on page 41
(RCC_CFGR).
Table 10: RCC - register map and reset
Section 5.2.6: Port bit reset register
(x=A..E). Embedded boot loader on page 32
11, Figure 12, Figure 13
DBGMCU_IDCODE on page
Section 4.3.1: Clock control register (RCC_CR)
modified. Bit definitions modified in
83. Wakeup latency description
Table 7: Stop mode.
reset value modified.
Section 16.13.3: ADC control register 2
Table 33: Watchdog timeout period (with 40 kHz
Figure 7: Clock
Section 16.2: Main
updated.
Section 16.10.9: Combined injected simultaneous +
Section 5.3.2: Using OSC_IN/OSC_OUT pins
PD0/PD1. Small text changes. Internal LSI RC frequency
Table 33: Watchdog timeout period (with 40
updated. Option byte addresses corrected in
and Table 2: Flash module
Section 2.3.4: Embedded Flash
Section 16: Analog-to-digital converter
Revision history
(TIMx_CR1).
486. Section 15.6: I2C
summary.
modified.
Section 4.3.1: Clock control
Section 4.3.2:
added.
and Figure 14 modified.
modified.
Section 5.2:
9.5.2 on page
updated.
clarified.
and Center-aligned
updated.
tree.
features.
Figure 2:
organization. Information block
memory.
(ADC)).
added.
values.
474.
133.
and
497/501