Figure 74. Counter Timing Diagram With Prescaler Division Change From 1 To 2 - ST STM32F101 Series Reference Manual

General purpose timer (TIMx)
The Time Base Unit includes:
Counter Register (TIMx_CNT)
Prescaler Register (TIMx_PSC):
Auto-Reload Register (TIMx_ARR)
The auto-reload register is preloaded. Writing or reading the auto-reload register access the
preload register. The content of the preload register is transferred in the shadow register
permanently or at each update event UEV, depending on the auto-reload preload enable bit
(ARPE) in TIMx_CR1 register. The update event is sent when the counter reaches the
overflow (or underflow when downcounting) and if the UDIS bit equals 0 in the TIMx_CR1
register. It can also be generated by software. The generation of the update event is
described in detail for each configuration.
The counter is clocked by the prescaler output CK_CNT, which is enabled only when the
counter enable bit (CEN) in TIMx_CR1 register is set (refer also to the slave mode controller
description to get more details on counter enabling).
Note that the actual counter enable signal CNT_EN is set 1 clock cycle after CEN.
Prescaler description
The prescaler can divide the counter clock frequency by any factor between 1 and 65536. It
is based on a 16-bit counter controlled through a 16-bit register (in the TIMx_PSC register).
It can be changed on the fly as this control register is buffered. The new prescaler ratio is
taken in account at the next update event.
Figure 74
ratio is changed on the fly:

Figure 74. Counter timing diagram with prescaler division change from 1 to 2

216/501
and Figure 75 give some examples of the counter behavior when the prescaler
CK_PSC
CNT_EN
Timer clock = CK_CNT
Counter register
Update event (UEV)
Prescaler control register
Write a new value in TIMx_PSC
Prescaler buffer
Prescaler counter
F7 F8 F9 FA FB FC 00
0
0
0 1
0
01 02 03
1
1
0 1 0 1 0 1
RM0008