Trise Register (I2C_Trise) - ST STM32F101 Series Reference Manual

RM0008
15.7.9

TRISE Register (I2C_TRISE)

Address offset: 0x20
Reset value: 0x0002
15 14 13 12
Bits 15:6 Reserved, forced by hardware to 0.
Bits 5:0 TRISE[5:0]: Maximum Rise Time in Fast/Standard mode (Master mode)
These bits must be programmed with the maximum SCL rise time given in the I
incremented by 1.
For instance: in standard mode, the maximum allowed SCL rise time is 1000 ns.
If, in the I2C_CR2 register, the value of FREQ[5:0] bits is equal to 08h and t
TRISE[5:0] bits must be programmed with 09h.
(1000 ns / 125 ns = 8 + 1)
The filter value can also be added to TRISE[5:0].
If the result is not an integer, TRISE[5:0] must be programmed with the integer part, in order to
respect the t
Note:
TRISE[5:0] must be configured only when the I2C is disabled (PE = 0).
11 10 9 8
Reserved
parameter.
HIGH
Inter-integrated circuit (I2C) interface
7 6 5 4
rw rw
3 2 1 0
TRISE[5:0]
rw rw rw rw
2
C bus specification,
= 125 ns therefore the
CK
345/501