Apb1 Peripheral Clock Enable Register (Rcc_Apb1Enr) - ST STM32F101 Series Reference Manual

RM0008
4.3.8

APB1 Peripheral Clock enable register (RCC_APB1ENR)

Address: 0x1C
Reset value: 0x0000 0000
Access: word, half-word and byte access
No wait state, except if the access occurs while an access to a peripheral on APB1 domain
is on going. In this case, wait states are inserted until this access to APB1 peripheral is
finished.
31 30 29 28
PWR
Reserved
EN
Res. rw
15 14 13 12
SPI2
Res. Reserved
EN
Res. rw Res.
Bits 31:29 Reserved, always read as 0.
Bit 28 PWREN Power interface clock enable
Set and reset by software.
0: Power interface clock disabled
1: Power interface clock enable
Bit 27 BKPEN Backup interface clock enable
Set and reset by software.
0: Backup interface clock disabled
1: Backup interface clock enabled
Bit 26 Reserved, always read as 0.
Bit 25 CANEN CAN clock enable
Set and reset by software.
0: CAN clock disabled
1: CAN clock enabled
Bit 24 Reserved, always read as 0.
Bit 23 USBEN USB clock enable
Set and reset by software.
0: USB clock disabled
1: USB clock enabled
Bit 22 I2C2EN I2C 2 clock enable
Set and reset by software.
0: I2C 2 clock disabled
1: I2C 2 clock enabled
Bit 21 I2C1EN I2C 1 clock enable
Set and reset by software.
0: I2C 1 clock disabled
1: I2C 1 clock enabled
27 26 25 24
BKP CAN
Res. Res.
EN EN
rw rw
11 10 9
WWD
GEN
rw
23 22 21
USB I2C2 I2C1
EN EN EN
rw rw rw
8 7 6 5
Reserved
Res.
Reset and clock control (RCC)
20 19 18 17
USART3 USART2
Reserved
EN EN
rw rw
4 3 2
TIM4 TIM3
EN EN
rw rw
16
Res.
1 0
TIM2
EN
rw
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