Hardware Flow Control; Figure 181. Hardware Flow Control Between 2 Usart; Figure 182. Rts Flow Control - ST STM32F101 Series Reference Manual

Universal synchronous asynchronous receiver transmitter (USART)
case of single byte reception, there will be separate error flag interrupt enable bit (EIE bit in
the USART_CR3 register), which if set will issue an interrupt after the current byte with
either of these errors.
19.3.14

Hardware flow control

It is possible to control the serial data flow between 2 devices by using the nCTS input and
the nRTS output. The

Figure 181. Hardware flow control between 2 USART

RTS and CTS flow control can be enabled independently by writing respectively RTSE and
CTSE bits to 1 (in the USART_CR3 register).
RTS flow control
If the RTS flow control is enabled (RTSE=1), then nRTS is asserted (tied low) as long as the
USART receiver is ready to receive a new data. When the receive register becomes empty,
nRTS is deasserted, indicating that the transmission is expected to stop at the end of the
current frame.
enabled.

Figure 182. RTS flow control

RX
nRTS
CTS flow control
If the CTS flow control is enabled (CTSE=1), then the transmitter checks the nCTS input
before transmitting the next frame. If nCTS is asserted (tied low), then the next data is
transmitted (assuming that a data is to be transmitted, in other words, if TXE=0), else the
transmission does not occur. When nCTS is deasserted during a transmission, the current
transmission is completed before the transmitter stops.
454/501
Figure 181
USART 1
TX
TX circuit
nCTS
RX
RX circuit
nRTS
Figure 182 shows an example of communication with RTS flow control
Start
Data 1
Bit
shows how to connect 2 devices in this mode:
RX
nRTS
TX
nCTS
Stop Idle Start
Bit Bit
Data 1 read
RXNE
Data 2 can now be transmitted
USART 2
RX circuit
TX circuit
Stop
Data 2
Bit
RXNE
RM0008