ST STM32F101 Series Reference Manual page 213

RM0008
Table 38. TIM1 - Register map and reset values (continued)
Offset Register
TIM1_CCMR2
Output Compare
mode
Reset value
1Ch
TIM1_CCMR2
Input Capture
mode
Reset value
TIM1_CCER
20h
Reset value
TIM1_CNT
24h
Reset value
TIM1_PSC
28h
Reset value
TIM1_ARR
2Ch
Reset value
TIM1_RCR
30h
Reset value
TIM1_CCR1
34h
Reset value
TIM1_CCR2
38h
Reset value
TIM1_CCR3
3Ch
Reset value
TIM1_CCR4
40h
Reset value
TIM1_BDTR
44h
Reset value
TIM1_DCR
48h
Reset value
TIM1_DMAR
4Ch
Reset value
Refer to
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Table 1 on page 27 for the register boundary addresses.
OC4M
[2:0]
0 0 0
IC4F[3:0]
0 0 0
0
0 0 0
0 0 0
0 0 0
Reserved
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
Advanced control timer (TIM1)
CC4S OC3M
[1:0] [2:0]
0 0 0 0 0 0 0 0 0
IC4
CC4S
PSC IC3F[3:0]
[1:0]
[1:0]
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
CNT[15:0]
0 0 0 0 0 0 0 0 0
PSC[15:0]
0 0 0 0 0 0 0 0 0
ARR[15:0]
0 0 0 0 0 0 0 0 0
REP[7:0]
0 0 0 0
CCR1[15:0]
0 0 0 0 0 0 0 0 0
CCR2[15:0]
0 0 0 0 0 0 0 0 0
CCR3[15:0]
0 0 0 0 0 0 0 0 0
CCR4[15:0]
0 0 0 0 0 0 0 0 0
LOCK
DT[7:0]
[1:0]
0 0 0 0 0 0 0 0 0
DBL[4:0]
Reserved
0 0 0 0 0 0
DMAB[15:0]
0 0 0 0 0 0 0 0 0
CC3S
[1:0]
0 0 0 0
IC3
CC3S
PSC
[1:0]
[1:0]
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
DBA[4:0]
0 0 0 0
0 0 0 0
213/501