ST STM32F101 Series Reference Manual page 189

RM0008
Bit 2 URS: Update request source.
This bit is set and cleared by software to select the UEV event sources.
0: Any of the following events generate an update interrupt or DMA request if enabled. These events
can be:
– Counter overflow/underflow
– Setting the UG bit
– Update generation through the slave mode controller
1: Only counter overflow/underflow generates an update interrupt or DMA request if enabled.
Bit 1 UDIS: Update disable.
This bit is set and cleared by software to enable/disable UEV event generation.
0: UEV enabled. The Update (UEV) event is generated by one of the following events:
– Counter overflow/underflow
– Setting the UG bit
– Update generation through the slave mode controller
Buffered registers are then loaded with their preload values.
1: UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC,
CCRx). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware
reset is received from the slave mode controller.
Bit 0 CEN: Counter enable.
0: Counter disabled
1: Counter enabled
Note: External clock, gated mode and encoder mode can work only if the CEN bit has been previously
set by software. However trigger mode can set the CEN bit automatically by hardware.
Advanced control timer (TIM1)
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