Capture/Compare Register 1 (Timx_Ccr1); Capture/Compare Register 2 (Timx_Ccr2) - ST STM32F101 Series Reference Manual

General purpose timer (TIMx)
13.5.13

Capture/compare register 1 (TIMx_CCR1)

Address offset: 0x34
Reset value: 0x0000
15 14 13
rw rw rw
Bits 15:0 CCR1[15:0]: Capture/Compare 1 Value).
If channel CC1 is configured as output:
CCR1 is the value to be loaded in the actual capture/compare 1 register (preload value).
It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register (bit
OC1PE). Else the preload value is copied in the active capture/compare 1 register when an update
event occurs.
The active capture/compare register contains the value to be compared to the counter TIMx_CNT and
signaled on OC1 output.
If channel CC1is configured as input:
CCR1 is the counter value transferred by the last input capture 1 event (IC1).
13.5.14

Capture/compare register 2 (TIMx_CCR2)

Address offset: 0x38
Reset value: 0x0000
15 14 13
rw rw rw
Bits 15:0 CCR2[15:0]: Capture/Compare 2 Value.
If channel CC2 is configured as output:
CCR2 is the value to be loaded in the actual capture/compare 2 register (preload value).
It is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register (bit
OC2PE). Else the preload value is copied in the active capture/compare 2 register when an update
event occurs.
The active capture/compare register contains the value to be compared to the counter TIMx_CNT and
signalled on OC2 output.
If channel CC2 is configured as input:
CCR2 is the counter value transferred by the last input capture 2 event (IC2).
268/501
12 11 10 9
rw rw rw rw
12 11 10 9
rw rw rw rw
8 7 6 5
CCR1[15:0]
rw rw rw rw
8 7 6 5
CCR2[15:0]
rw rw rw rw
4 3 2 1
rw rw rw rw
4 3 2 1
rw rw rw rw
RM0008
0
rw
0
rw