I2C Register Map; Table 47. I2C Register Map And Reset Values - ST STM32F101 Series Reference Manual

Inter-integrated circuit (I2C) interface
2
15.8 I C register map
2
Table 47. I C register map and reset values
Offset Register
I2C_CR1
00h
Reset value
I2C_CR2
04h
Reset value
I2C_OAR1
08h
Reset value
I2C_OAR2
0Ch
Reset value
I2C_DR
10h
Reset value
I2C_SR1
14h
Reset value
I2C_SR2
18h
Reset value
I2C_CCR
1Ch
Reset value
I2C_TRISE
20h
Reset value
Refer to
346/501
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Table 1 on page 27 for the register boundary addresses.
0 0 0
0
Reserved
0 1
Reserved
Reserved
0 0 0
PEC[7:0]
0 0 0 0
0 0
Reserved
0 0 0 0 0 0 0 0
FREQ[5:0]
0 0 0 0 0 0
ADD[9:8] ADD[7:1]
0 0 0 0 0 0
ADD2[7:1]
0 0 0 0
DR[7:0]
0 0 0 0
0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
CCR[11:0]
0 0 0 0 0 0 0 0
TRISE[5:0]
0 0
RM0008
0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0
0 0 0 0
0 0 1 0