Adc Injected Channel Data Offset Register X (Adc_Jofrx)(X=1; Adc Watchdog High Threshold Register (Adc_Htr) - ST STM32F101 Series Reference Manual

RM0008
16.13.6

ADC injected channel data offset register x (ADC_JOFRx)(x=1..4)

Address offset: 0x14-0x20
Reset value: 0x0000 0000
31 30 29 28
15 14 13 12
Reserved
Bits 31:12 Reserved, must be kept cleared.
Bits 11:0 JOFFSETx[11:0]: Data offset for injected channel x
These bits are written by software to define the offset to be subtracted from the raw converted data
when converting injected channels. The conversion result can be read from in the ADC_JDRx
registers.
16.13.7

ADC watchdog high threshold register (ADC_HTR)

Address offset: 0x24
Reset value: 0x0000 0000
31 30 29 28
15 14 13 12
Reserved
Bits 31:12 Reserved, must be kept cleared.
Bits 11:0 HT[11:0] Analog watchdog high threshold
These bits are written by software to define the high threshold for the Analog Watchdog.
27 26 25 24
Reserved
11 10 9 8
rw rw rw rw
27 26 25 24
Reserved
11 10 9 8
rw rw rw rw
Analog-to-digital converter (ADC)
23 22 21 20
7 6 5 4
JOFFSETx[11:0]
rw rw rw rw
23 22 21 20
7 6 5 4
HT[11:0]
rw rw rw rw
19 18 17 16
3 2 1 0
rw rw rw rw
19 18 17 16
3 2 1 0
rw rw rw rw
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