Figure 7. Clock Tree - ST STM32F101 Series Reference Manual

RM0008
Each clock source can be switched on or off independently when it is not used, to optimize
power consumption.
Figure 7. Clock tree
8 MHz
HSI RC
PLLSRC
OSC_OUT
4-16 MHz
HSE OSC
OSC_IN
OSC32_IN
LSE OSC
32.768 kHz
OSC32_OUT
LSI RC
40 kHz
Main
Clock Output
MCO
1. When the HSI is used as a PLL clock input, the maximum system clock frequency that can be achieved is
64 MHz.
Several prescalers allow the configuration of the AHB frequency, the high speed APB
(APB2) and the low speed APB (APB1) domains. The AHB and the APB2 domains
maximum frequency is 72 MHz. The APB1 domains maximum allowed frequency is 36
MHz. The RCC feeds the Cortex System Timer (SysTick) external clock with the AHB clock
divided by 8. The SysTick can work either with this clock or with the Cortex clock (AHB),
configurable in the SysTick Control and Status Register. The ADCs are clocked by the clock
of the High Speed domain (APB2) divided by 2, 4, 6 or 8.
HSI
/2
SW
PLLMUL
HSI
..., x16
x2, x3, x4
PLLCLK
PLL
HSE
CSS
PLLXTPRE
/2
/128
LSE
RTCCLK
RTCSEL[1:0]
to Independent Watchdog (IWDG)
LSI
/2
PLLCLK
HSI
HSE
SYSCLK
MCO
USB
Prescaler
/1, 1.5
72 MHz max
/8
AHB APB1
SYSCLK
Prescaler Prescaler
72 MHz
/1, 2..512 /1, 2, 4, 8, 16
max
TIM2, 3, 4
x1, 2 Multiplier
APB2
Prescaler
/1, 2, 4, 8, 16
TIM1 Timer
x1, 2 Multiplier
to RTC
IWDGCLK
Reset and clock control (RCC)
USBCLK
48 MHz
to USB interface
HCLK
to AHB bus, core,
memory and DMA
Clock
Enable (3 bits)
to Cortex System timer
FCLK Cortex
free running clock
36 MHz max
Peripheral Clock
Enable (13 bits)
Peripheral Clock
Enable (3 bits)
72 MHz max
Peripheral Clock
Enable (11 bits)
Peripheral Clock
Enable (1 bit)
ADC
Prescaler
ADCCLK
/2, 4, 6, 8
Legend:
HSE = High Speed External clock signal
HSI = High Speed Internal clock signal
LSI = Low Speed Internal clock signal
LSE = Low Speed External clock signal
PCLK1
to APB1
peripherals
to TIM2, 3
and 4
TIMXCLK
PCLK2
to APB2
peripherals
to TIM1
TIM1CLK
to ADC
49/501