Clock Control Register (I2C_Ccr) - ST STM32F101 Series Reference Manual

Inter-integrated circuit (I2C) interface
Bit 0 MSL: Master/Slave
0: Slave Mode
1: Master Mode
– Set by hardware as soon as the interface is in Master mode (SB=1).
– Cleared by hardware after detecting a Stop condition on the bus or a loss of arbitration (ARLO=1), or
by hardware when PE=0.
15.7.8

Clock control register (I2C_CCR)

Address offset: 0x1C
Reset value: 0x0000
15 14 13 12
F/S DUTY Reserved
rw rw
Bit 15 F/S I 2
C Master Mode Selection
0: Standard Mode I2C
1: Fast Mode I2C
Bit 14 DUTY Fast Mode Duty Cycle
0: Fast Mode t
1: Fast Mode t
Bits 13:12 Reserved, forced by hardware to 0.
Bits 11:0 CCR[11:0] Clock Control Register in Fast/Standard mode (Master mode)
Controls the SCL clock in master mode.
Standard Mode or SMBus:
T = CCR * T
high
T = CCR * T
ow
Fast Mode:
If DUTY = 0:
T = CCR * T
high
T = 2 * CCR * T
ow
If DUTY = 1: (to reach 400 kHz)
T = 9 * CCR * T
high
T = 16 * CCR * T
ow
For instance: in standard mode, to generate a 100kHz SCL frequency:
If FREQR = 08, T
(28h <=> 40d x 125ns = 5000 ns.)
Notes:
1. The minimum allowed value is 04h, except in FAST DUTY mode where the minimum allowed value
is 01h
2. t includes the SCLH rising edge
high
3. t includes the SCLH falling edge
low
4. These timings are without filters.
344/501
11 10 9 8
rw rw rw rw
/t = 2
low high
/t = 16/9 (see CCR)
low high
CK
CK
CK
CK
CK
CK
= 125ns so CCR must be programmed with 28h
ck
7 6 5 4
CCR[11:0]
rw rw rw rw
RM0008
3 2 1 0
rw rw rw rw