System Clock (Sysclk) Selection; Clock Security System (Css); Clock Security System For Lse Clock (Lsecss) - ST STM32C0 Series Getting Started

2.5

System clock (SYSCLK) selection

One of the following clocks can be selected as system clock (SYSCLK):
• LSI
• LSE
• HSISYS
• HSE
The maximum frequency of the system clock is 48 MHz. Upon system reset, the HSISYS clock derived from the
HSI48 oscillator is selected as system clock. When a clock source is used as a system clock, it is not possible to
stop it.
A switch from one clock source to another occurs only if the target clock source is ready (clock stable after startup
delay). If a clock source that is not yet ready is selected, the switch occurs when the clock source becomes ready.
Status bits in the internal clock sources calibration register (RCC_ICSCR) indicate which clock(s) is (are) ready
and which clock is currently used as a system clock.
2.6

Clock security system (CSS)

Software can activate the clock security system. In this case, the clock detector is enabled after the HSE oscillator
startup delay. It is disabled when this oscillator is stopped.
If a failure is detected on the HSE clock:
• the HSE oscillator is automatically disabled
• a clock failure event is sent to the break input of TIM1, TIM16, and TIM17 timers
• CSSI (clock security system interrupt) is generated
The CSSI is linked to the Cortex
aware of an HSE clock failure to allow it to perform rescue operations.
Note: If the CSS is enabled and the HSE clock fails, the CSSI occurs and an NMI is automatically generated. The NMI
is executed infinitely unless the CSS interrupt pending bit is cleared. It is therefore necessary that the NMI ISR
clears the CSSI by setting the CSSC bit in the clock interrupt clear register (RCC_CICR).
If HSE is selected directly or indirectly as system clock, and a failure of the HSE clock is detected, the system
clock switches automatically to HSISYS and the HSE oscillator is disabled.
2.7

Clock security system for LSE clock (LSECSS)

A clock security system on LSE can be activated by setting the LSECSSON bit in Control register 1
(RCC_CSR1). This bit can be cleared only by a hardware reset or RTC software reset, or after LSE clock failure
detection. LSECSSON must be written after LSE and LSI are enabled (LSEON and LSION enabled) and ready
(LSERDY and LSIRDY flags set by hardware), and after selecting the RTC clock by RTCSEL.
The LSECSS works in all modes except Standby and Shutdown. It keeps working also under system reset
(excluding power-on reset). If a failure is detected on the LSE oscillator, the LSE clock is no longer supplied to the
RTC, but its registers are not impacted.
Note: If the LSECSS is enabled and the LSE clock fails, the LSECSSI occurs and an NMI is automatically generated.
The NMI is executed infinitely unless the LSECSS interrupt pending bit is cleared. It is therefore necessary that
the NMI ISR clears the LSECSSI by setting the LSECSSC bit in the clock interrupt clear register (RCC_CICR).
If LSE is used as system clock, and a failure of LSE clock is detected, the system clock switches automatically
to LSI. In low-power modes, an LSE clock failure generates a wake-up. The interrupt flag must then be cleared
within the RCC registers.
The software must then disable the LSECSSON bit, stop the defective 32 kHz oscillator (by clearing LSEON), and
change the RTC clock source (no clock, LSI or HSE, with RTCSEL), or take any appropriate action to secure the
application.
The frequency of the LSE oscillator must exceed 30 kHz to avoid false positive detections.
AN5673 - Rev 2
®
-M0+ NMI (nonmaskable interrupt) exception vector. It makes the software
AN5673
System clock (SYSCLK) selection
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