ST STM32F101 Series Reference Manual page 44

Power control (PWR)
Bit 1 PDDS: Power Down Deepsleep.
This bit is set and cleared by software. It works together with the LPDS bit.
0: Enter Stop mode when the CPU enters Deepsleep. The regulator status depends on the LPDS bit.
1: Enter Standby mode when the CPU enters Deepsleep.
Bit 0 LPDS: Low-Power Deepsleep.
This bit is set and cleared by software. It works together with the PDDS bit. 0: Voltage regulator on
during Stop mode
1: Voltage regulator in low-power mode during Stop mode
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