Figure 138. Transfer Sequence Diagram For Master Transmitter - ST STM32F101 Series Reference Manual

RM0008
Closing the communication
After writing the last byte to the DR register, the STOP bit is set by software to generate a
Stop condition (see
automatically back to slave mode (M/SL bit cleared).
Note: Stop condition should be programmed during EV8_2 event, when either TxE or BTF is set.

Figure 138. Transfer sequence diagram for master transmitter

7-bit Master Transmitter:
S Address
EV5
10-bit Master Transmitter
S
EV5
Legend: S= Start, S
EVx= Event (with interrupt if ITEVFEN=1)
EV5: SB=1, cleared by reading SR1 register followed by writing DR register with Address.
EV6: ADDR=1, cleared by reading SR1 register followed by reading SR2.
EV8_1: TxE=1 shift register empty
EV8: TxE=1 cleared by writing DR register.
EV8_2: TxE=1, BTF = 1 cleared by HW by stop condition
EV9: ADD10=1, cleared by reading SR1 register followed by writing DR register.
Figure 138
A
EV6 EV8_1
Header A Address
EV9
= Repeated Start, P= Stop, A= Acknowledge, NA= Non-acknowledge,
r
Inter-integrated circuit (I2C) interface
Transfer sequencing EV8_2). The interface goes
Data1 A Data2
EV8 EV8
A Data1
EV6 EV8_1 EV8
A DataN
.....
EV8
A DataN
.....
EV8
A P
EV8_2
A P
EV8_2
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