ST STM32F101 Series Reference Manual page 498

Revision history
Table 87.
Date
20-Nov-2007
498/501
Document revision history (continued)
Revision
Figure 165: USART block diagram
Procedure modified in
In Section 19.3.5: Fractional baud rate
– Equation legend modified
– Table 67: Error calculation for programmed baud rates
– Note added
Small text changes. In
bit 15 is reserved.
Flash memory organization corrected,
modified in
Note added below
supplies.
RTCSEL[1:0] bit description modified in
control register
Names of bits [0:2] corrected for RCC_APB1RSTR and RCC_APB1ENR
in Table 10: RCC - register map and reset
Impedance value specified in
page 495.
In Section 18.4.1: SPI Control Register 1
corrected.
Prescaler buffer behavior specified when an update event occurs (see
upcounting mode on page
Center-aligned mode (up/down counting) on page
AWDCH[4:0] modified in
(ADC_CR1)
time register 1
2
CAN_BTR bit 8 is reserved in
values. CAN master control register (CAN_MCR) on page 292
V range corrected in
REF+
on page 34.
Start condition on page 323
alternate function
function remapping.
In Section 5.4.2: AF remap and debug I/O configuration register
(AFIO_MAPR), bit definition modified for USART2_REMAP = 0. In
Section 5.4.3: External interrupt configuration register 1
(AFIO_EXTICR1), bit definition modified for SPI1_REMAP = 0.
In Table 85: Important TPIU
supported.
TRACE port size setting corrected in
page 489. Figure
modified. Figure 10: Basic structure of a five-volt tolerant I/O port bit
added.
Table 5.3.1: Using OSC32_IN/OSC32_OUT pins as GPIO ports
PC14/PC15 on page 88
Bit descriptions modified in
JTAG ID code corrected in
Modified: Section 11.2: Main
Tamper detection,
description,
Battery backup
ASOE bit description modified in
register (BKP_RTCCR).
Changes
modified.
Character reception on page
CAN bit timing register (CAN_BTR) on page
Section 2.3.4: Embedded Flash
Figure 3: Power supply overview
(RCC_BDCR).
A.4: Voltage glitch on ADC input 0 on
217, Downcounting mode on page 220
Section 16.13.2: ADC control register 1
and bits [26:24] are reserved in
(ADC_SMPR1).
Table 44: bxCAN - register map and reset
Table 48: ADC pins
updated. Note removed in
remapping. Note added in
registers, at 0xE0040004, bit2 set is not
9, Figure 11, Figure
added.
Section 8.4.5
Section 20.6.2: TMC TAP on page 475
features,
Section 9.4: RTC
Controlling the downcounter: on page
domain, Section 8.1:
Section 9.5.2: RTC clock calibration
437.
generation:
modified
Table 2: Flash module organization
memory.
in Section 3.1: Power
Section 4.3.9: Backup domain
values.
(SPI_CR1), BR[2:0] description
222).
Section 16.13.4: ADC sample
and in On 100-pin packages
Table 13: BXCAN
Table 16: Timer 4 alternate
TPUI TRACE pin assignment on
12, Figure 13 and Figure 14
and Section 8.4.6.
Section 9.2: Features,
calibration, Section 17.4: Functional
144, Section 3.1.2:
Introduction.
RM0008
302,
and
corrected.
.
Section 9.3: