Figure 37. Counter Timing Diagram, Internal Clock Divided By N; Figure 38. Counter Timing Diagram, Update Event When Repetition Counter Is Not Used - ST STM32F101 Series Reference Manual

Advanced control timer (TIM1)

Figure 37. Counter timing diagram, internal clock divided by N

Figure 38. Counter timing diagram, update event when repetition counter is not
Center-aligned mode (up/down counting)
In center-aligned mode, the counter counts from 0 to the auto-reload value (content of the
TIM1_ARR register) – 1, generates a counter overflow event, then counts from the auto-
reload value down to 1 and generates a counter underflow event. Then it restarts counting
from 0.
In this mode, the DIR direction bit in the TIM1_CR1 register cannot be written. It is updated
by hardware and gives the current direction of the counter.
The update event can be generated at each counter overflow and at each counter underflow
or by setting the UG bit in the TIM1_EGR register (by software or by using the slave mode
controller) also generates an update event. In this case, the counter restarts counting from
0, as well as the counter of the prescaler.
The UEV update event can be disabled by software by setting the UDIS bit in the TIM1_CR1
register. This is to avoid updating the shadow registers while writing new values in the
preload registers. Then no update event occurs until UDIS bit has been written to 0.
However, the counter continues counting up and down, based on the current auto-reload
value.
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CK_PSC
Timer clock = CK_CNT
Counter register
Counter underflow
Update event (UEV)
Update interrupt flag (UIF)
used
CK_PSC
CNT_EN
Timer clock = CK_CNT
Counter register
Counter underflow
Update event (UEV)
Update interrupt flag (UIF)
Auto-reload register
Write a new value in TIM1_ARR
20
1F 00
05 04 03 02 01 00 36 35 34 33 32 31 30 2F
FF
RM0008
36
36